4.4. Field-Oriented Control (FOC)

FOC consists of a velocity controller, a current controller, and commutation and estimation subcomponents. A high-level block diagram of the FOC components is shown in Figure 4.3.

../_images/accret-bdiag.svg

Figure 4.3 Block diagram of MCAF Field Oriented Control

This diagram shows a number of features that are described in the test harness.

4.4.1. Velocity Control

The velocity control loop is a straightforward, scalar PI controller, with managed saturation features to prevent integrator windup when either the velocity or current controller saturates.

It is preceded by a rate limiter, to provide more gentle trajectory shaping and reduce transient overshoot.

Saturation and antiwindup features are present and covered in a separate document.

4.4.2. Current Control

The current control loop is a vector control loop that operates in the dq reference frame, with reference transforms to convert to/from the ABC stationary reference frame in which currents are measured and duty cycles are commanded. The vector control loop itself is a straightforward pair of PI controllers, with managed saturation features to prevent integrator windup when the current controller saturates. (Saturation and antiwindup features are covered in more detail in a separate document.)

Figure 4.3 shows a filter block preceding the current controller. It is intended to slow down incoming commands from the velocity loop, which typically executes at a slower rate.

Figure 4.3 also shows DC link voltage compensation following the Inverse Park Transform.

4.4.3. Position and Velocity Estimator

MCAF provides several position and velocity estimators used for commutation and velocity control:

4.4.4. Implementation Notes

4.4.4.1. FOC feature support

4.4.4.1.1. Flux weakening

In MCAF R1-R5, flux weakening was not provided, and the velocity controller set the d-axis current command to zero.

In MCAF R6, flux weakening has been provided as part of the Flux control module.

4.4.4.1.2. Current command prefilter

The filter just prior to the current controller is unimplemented in MCAF R1-R6, but is reserved for a future version.

4.4.4.1.4. PWM duty cycle realization

MCAF R1 used an implementation of conventional space-vector PWM (CSVPWM) from the Microchip Motor Control Library (MC_CalculateSpaceVectorPhaseShifted_Assembly). Starting with MCAF R2, this has been switched to use a Zero Sequence Modulation block, which includes clipping within realizable limits (minimum and maximum duty cycle limits) in order to support overmodulation. See MCAF_FocStepIsrForwardPath().

For more information on ZSM, see Microchip’s Zero Sequence Modulation Tutorial.

4.4.4.1.5. Velocity loop current limit

The velocity loop controller has upper and lower limits for its output, a q-axis current reference.

MCAF R1 - R5 used fixed upper and lower limits, equal to \(\plusmn I_{\max}\), the rated continuous drive current or rated continuous motor current, whichever is loewr.

MCAF R6 uses a limit computed by the flux control module, that is bounded by \(\plusmn I_{\max}\). Depending on the type of current limit region used, this limit may be fixed or may be changing dynamically. For more details, see Calculation of q-axis current limit.

4.4.4.1.6. Saturation and anti-windup

Velocity loop error integration is inhibited when certain velocity anti-windup conditions occur.

In MCAF R1 - R5, velocity anti-windup conditions include detection of current and voltage saturation.

In MCAF R6, voltage saturation is not used for velocity anti-windup, when flux weakening is enabled, to allow entry into the flux-weakening region. When flux weakening is disabled, voltage saturation is used for velocity anti-windup.

4.4.4.1.7. Flux control

Flux control, including flux weakening and MTPA, was added as an option in MCAF R6.

4.4.4.1.8. Dead-time compensation

Dead-time compensation was added as an option in MCAF R6.

4.4.4.2. Numerical values for PWM duty cycle and dead time

It is important to understand some of the subtleties of PWM duty cycle in MCAF, in the presence of dead time. Interpretation of particular numeric duty cycles (for example, d = 0.1) can be slightly tricky. This section documents how they are used, and how to determine the correct values given known limits of the power electronics. Figure 4.4 shows several important points related to PWM duty cycle and dead time.

../_images/pwm-with-deadtime.svg

Figure 4.4 Interpreting duty cycle correctly

A typical PWM peripheral for use with a half-bridge circuit produces three waveforms:

  • a raw generated pulse waveform G with duty cycle \(D\)
  • high-side output H with the leading edge delayed by dead time \(\delta_1\),
  • low-side output L inverted and with the trailing edge delayed by dead time \(\delta_1\).

Other implementations may split dead time in half symmetrically. (see note on dsPIC33 PWM)

  • The intended duty cycle of the entire half-bridge is \(D\).
  • The duty cycle of the high-side gate drive is \(D-\delta_1\). (with \(\delta_1\) expressed as a fraction of total PWM period)
  • The duty cycle of the low-side gate drive is \(1-D-\delta_1\).
  • With inductive loads, and transistor on-time and off-time roughly equal, the effective duty cycle of the entire half bridge is
    • \(D-\delta_1\) if current is flowing out of the half bridge (the low-side diode conducts during dead time),
    • \(D+\delta_1\) if current is flowing into the half bridge (the high-side diode conducts during dead time),
    • or somewhere in between if current does not stay positive or negative during the entire dead time — this represents discontinuous conduction.

Circuit designers of the half bridge should record the following quantities:

  • Minimum duty cycle \(D_{HMIN}\) and maximum duty cycle \(D_{HMAX}\) of the high-side transistor
  • Minimum duty cycle \(D_{LMIN}\) and maximum duty cycle \(D_{LMAX}\) of the low-side transistor
  • Desired dead time \(\delta_1\)

The relevant parameters that should be entered into motorBench® Development Suite are:

  • Minimum duty cycle of the bridge \(D_{BMIN}=\max(D_{HMIN},1-D_{LMAX}-2\delta_1)\)
  • Maximum duty cycle of the bridge \(D_{BMAX}=\min(1-D_{HMIN},D_{HMAX}+2\delta_1)\)

This will produce the range of duty cycles shown in Table 4.1.

Table 4.1 Duty cycle ranges for PWM waveforms
Waveform Minimum duty cycle Maximum duty cycle
G \(D_{BMIN} + \delta_1\) \(D_{BMAX} - \delta_1\)
H \(D_{BMIN}\) \(D_{BMAX} - 2\delta_1\)
L \(1-D_{BMAX}\) \(1-D_{BMIN} - 2\delta_1\)

Usually the two minimum duty cycles \(D_{LMIN}\) and \(D_{HMIN}\) determine the duty cycle limits, not the maximum duty cycles.

To help clarify how this works, some concrete examples are given below.

4.4.4.2.1. PWM peripheral in dsPIC33 devices

The PWM peripheral in dsPIC33EP parts splits the dead time in half, calculating edges for the low-side and high-side outputs so that they are centered in time around the “ideal” switching instant if there were no dead time. The widths of waveforms G, H, and L in Figure 4.4 are the same, but waveforms H and L are advanced in time by \(\delta_1/2\).

4.4.4.2.2. Example 1

  • High-side transistor must be limited between \(D_{HMIN}=1.2\%\) duty cycle and \(D_{HMAX} = 99\%\) duty cycle
  • Low-side transistor must be limited between \(D_{LMIN}=3.0\%\) duty cycle and \(D_{LMAX} = 99.5\%\) duty cycle
  • Dead time of 2%

This is a realistic case for a bootstrap gate drive, where \(D_{LMIN}\) is larger, to ensure adequate recharge time of the bootstrap capacitors.

We calculate

(4.3)\[\begin{aligned} D_{BMIN} &= \max(0.012, 1 - 0.995 - 0.04) = 0.012 \cr D_{BMAX} &= \min (1 - 0.03, 0.99 + 0.04) = 0.97 \end{aligned}\]

The waveform values produced by this are shown in Table 4.2.

Table 4.2 Duty cycle ranges for Example 1
Waveform Minimum duty cycle Maximum duty cycle
G 0.032 0.95
H 0.012 0.93
L 0.03 0.948

Note that in this case, the limits are determined by the minimum duty cycles; the maximum duty cycles of the H and L waveforms are comfortably below their required maximum.

4.4.4.2.3. Example 2

  • High-side transistor must be limited between \(D_{HMIN} = 1.2\%\) duty cycle and \(D_{HMAX} = 90\%\) duty cycle
  • Low-side transistor must be limited between \(D_{LMIN} = 3.0\%\) duty cycle and \(D_{LMAX} = 80\%\) duty cycle
  • Dead time of 2%

We calculate

(4.4)\[\begin{aligned} D_{BMIN} &= \max(0.012, 1 - 0.8 - 0.04) = 0.16 \cr D_{BMAX} &= \min (1 - 0.03, 0.9 + 0.04) = 0.94 \end{aligned}\]

The waveform values produced by this are shown in shown in Table 4.3.

Table 4.3 Duty cycle ranges for Example 2
Waveform Minimum duty cycle Maximum duty cycle
G 0.18 0.92
H 0.16 0.90
L 0.06 0.80

In this case, the limits are determined by the maximum duty cycles; the minimum duty cycles of the H and L waveforms are comfortably above their required minimum.

4.4.4.2.5. Affected source code files

Since MCAF R3, the generated file parameters/hal_params.h contains #define symbols to determine minimum and maximum duty cycles. There is also a comment that appears as follows:

Listing 4.1 parameters/hal_params.h
/*
 * Minimum and maximum duty cycles,
 * from the perspective of the PWM duty cycle registers.
 *
 * The actual minimum and maximum duty cycles created by the PWM generators
 * will have dead time (=0.04) added and subtracted.
 *
 * NOTE: this assumes identical dead time,
 * and no significant difference in propagation delay between gate drive channels.
 *
 * Effective limits for duty cycle as seen on the PWM outputs:
 * Minimum duty cycle on PWMxH: 0.005
 * Minimum duty cycle on PWMxL: 0.0223
 * Maximum duty cycle on PWMxH: 0.8977
 * Maximum duty cycle on PWMxL: 0.915
 */

/* The minimum duty cycle of the half-bridge affects
 * the minimum duty cycle of upper transistors
 * and maximum duty cycle of lower transistors.
 */
/* Minimum duty cycle register value in counts */
#define HAL_PARAM_MIN_DUTY_COUNTS             157      // Q0(157.00000)  =  +44.85714 m           =  +45.00000 m           - 0.3175%
/* Minimum duty cycle register value, as ratio */
#define HAL_PARAM_MIN_DUTY_Q15               1475      // Q15(  0.04501) =  +45.01343 m           =  +45.00000 m           + 0.0298%
/* Maximum low-side duty cycle register value in counts */
#define HAL_PARAM_MAX_LOWER_DUTY_COUNTS       3342      // Q0(3342.00000) = +954.85714 m           = +955.00000 m           - 0.0150%


/* The maximum duty cycle of the half-bridge affects
 * the maximum duty cycle of upper transistors
 * and minimum duty cycle of lower transistors.
 */
/* Maximum duty cycle register value in counts */
#define HAL_PARAM_MAX_DUTY_COUNTS            3282      // Q0(3282.00000) = +937.71429 m           = +937.70000 m           + 0.0015%
/* Maximum duty cycle register value, as ratio */
#define HAL_PARAM_MAX_DUTY_Q15              30727      // Q15(  0.93771) = +937.71362 m           = +937.70000 m           + 0.0015%
/* Minimum low-side duty cycle register value in counts */
#define HAL_PARAM_MIN_LOWER_DUTY_COUNTS        218      // Q0(218.00000)  =  +62.28571 m           =  +62.30000 m           - 0.0229%

4.4.4.2.6. Support for full on/off time in MCAF

MCAF does not support full on-time or off-time of either high-side or low-side transistor. This is a tricky feature to implement, because it represents a small jump discontinuity of the intended duty cycle.

4.4.4.3. Modules

4.4.4.3.1. Core FOC

Module Files Description Comments
parameters/deadtimecomp_params
parameters/deadtimecomp_params.h
parameters/foc_params
parameters/foc_params.h
 FOC control parameters
parameters/init_params
parameters/init_params.c
parameters/init_params.h
 Initialization of FOC control parameters
parameters/sat_PI_params
parameters/sat_PI_params.h
 PI Saturation parameters
deadtimecomp
deadtimecomp.c
deadtimecomp.h
deadtimecomp_types.h
 Dead-time compensation
foc
foc.c
foc.h
foc_types.h
 Top-level FOC These functions are called from the state machine modules, as described in the implementation notes.
sat_PI
sat_PI.c
sat_PI.h
sat_PI_types.h
 PI loop saturation management

4.4.4.3.2. Commutation

Module Files Description Comments
commutation/atpll
commutation/atpll.c
commutation/atpll.h
 Angle-tracking Phase-locked Loop (ATPLL)
commutation/common
commutation/common.h
 Common features used in all estimators
commutation/pll
commutation/pll.c
commutation/pll.h
 AN1292 Phase-locked Loop (PLL)
commutation/qei
commutation/qei.c
commutation/qei.h
commutation/qei_types.h
 Quadrature encoder support The quadrature encoder can be used as the primary estimator for commutation and velocity feedback, or to obtain a reference position and velocity for testing estimator performance.
commutation/qei_sync
commutation/qei_sync.c
commutation/qei_sync.h
commutation/qei_sync_types.h
 Back-EMF synchronization
parameters/atpll_params
parameters/atpll_params.h
parameters/pll_params
parameters/pll_params.h
 PLL estimator parameters
commutation
commutation.c
commutation.h
commutation_types.h
 Top-level commutation / estimation