6.6. Resource Usage¶
This section provides reference data for resource usage, covering program and data memory and CPU usage.
Please note: Resource usage is dependent on a number of factors, and may be different than the data shown below. These factors include:
- Compiler version
- Compiler optimization levels
- Compiler flags
- Settings in motorBench® Development Suite
- Settings in MCC
- MCAF parameter values
6.6.1. Test case¶
In each case described below, MCAF firmware packages were used
with their default settings and the AN1292 PLL estimator selected, for the Nidec Hurst DMA0204024B101 motor used with the dsPICDEM® MCLV‑2 Development Board.
The source code was built using XC16 with -O1 and -O2
compilation levels for the dsPIC33EP256MC506, and with MCAF_TEST_PROFILING and MCAF_TEST_HARNESS enabled.
6.6.1.1. Program and data memory¶
Resource usage statistics for program and data memory were derived from the map file.
6.6.1.2. CPU usage¶
CPU usage was determined with variants of MCAF modified to transmit CPU cycle count data via the UART, at various points in the motor control ISR, for a 20 kHz PWM ISR, using the dsPIC33EP256MC506 running at 70 MIPS, and dsPIC33CK256MP508 running at 100 MIPS.
CPU cycle count was measured over approximately 4 seconds, with the motor starting up, running, and slowing to a stop. The resulting time inside the motor control ISR was sorted from low to high, with the worst-case and 99.9% percentile computed. For example, 4 seconds of data at 20 kHz represents 80,000 data points, so the 99.9% percentile represents the 80th-highest sample of CPU usage. This represents conservative estimates of CPU usage for estimating remaining CPU capacity in aggregate over time, and exclude timing spikes which may occur when long execution paths coincide in the same ISR cycle. The worst-case CPU usage should be used to determine that the ISR does not overrun available time limits. Variation in CPU time is due to a number of factors, including:
- Branches (
ifstatements) may take alternate and unequal execution paths - Some algorithms run at submultiples of the ISR, so for example the PLL position estimator has a portion of code that runs once every 8 ISR cycles
- During different states of the state machine, different parts of the code are enabled or disabled
Main loop CPU usage was not profiled but is minimal (estimated at < 0.1 MIPS); not much code runs in the main loop.
6.6.2. Usage statistics for MCAF R3¶
| Statistic | MCAF R3, XC16 1.35 -O1 |
MCAF R3, XC16 1.35 -O2 |
|---|---|---|
| Program memory (bytes) | ||
| Excluding X2Cscope | 20367 | 21744 |
| X2Cscope module | 12831 | 12831 |
| Total | 33198 | 34575 |
| Data memory (bytes) | ||
| Excluding X2Cscope | 1342 | 1340 |
| X2Cscope module | 5466 | 5466 |
| Total | 6808 | 6806 |
| CPU ISR usage (% at 70 MIPS, 20 kHz ISR) | ||
| Worst-case | 64.1% | 62.9% |
| 99.9% percentile | 63.8% | 62.6% |
6.6.3. Usage statistics for MCAF R4¶
| Statistic | MCAF R4, XC16 1.36b -O1 |
MCAF R4, XC16 1.36b -O2 |
|---|---|---|
| Program memory (bytes) | ||
| Excluding X2Cscope | 17556 | 18150 |
| X2Cscope module | 12831 | 12753 |
| Total | 30309 | 30903 |
| Data memory (bytes) | ||
| Excluding X2Cscope | 1402 | 1402 |
| X2Cscope module | 5448 | 5448 |
| Total | 6850 | 6850 |
| CPU ISR usage (% at 70 MIPS, 20 kHz ISR) | ||
| Worst-case | 58.9% | 58.1% |
| 99.9% percentile | 58.9% | 58.1% |
6.6.4. Usage statistics for MCAF R5¶
| Statistic | MCAF R5, XC16 1.41 -O1 |
MCAF R5, XC16 1.41 -O2 |
|---|---|---|
| Program memory (bytes) | ||
| Excluding X2Cscope | 17334 | 18783 |
| X2Cscope module | 11709 | 11709 |
| Total | 29043 | 30492 |
| Data memory (bytes) | ||
| Excluding X2Cscope | 1528 | 1580 |
| X2Cscope module | 5186 | 5186 |
| Total | 6714 | 6766 |
| CPU ISR usage (% at 70 MIPS, 20 kHz ISR) | ||
| Worst-case | 58.3% | 57.6% |
| 99.9% percentile | 57.8% | 57.0% |
6.6.5. Usage statistics for MCAF R6¶
dsPIC33EP256MC506
| Statistic | MCAF R6, XC16 1.60 -O1 |
MCAF R6, XC16 1.60 -O2 |
|---|---|---|
| Program memory (bytes) | ||
| Excluding X2Cscope | 17376 | 18219 |
| X2Cscope module | 11709 | 11709 |
| Total | 29916 | 30885 |
| Data memory (bytes) | ||
| Excluding X2Cscope | 1672 | 1672 |
| X2Cscope module | 5186 | 5186 |
| Total | 6858 | 6858 |
| CPU ISR usage (approximate number of cycles, and percentage at 70 MIPS, 20 kHz ISR) | ||
| Worst-case | 2330 (66.5%) | 2280 (65.2%) |
| 99.9% percentile | 2300 (65.8%) | 2260 (64.6%) |
dsPIC33CK256MP508
| Statistic | MCAF R6, XC16 1.60 -O1 |
MCAF R6, XC16 1.60 -O2 |
|---|---|---|
| Program memory (bytes) | ||
| Excluding X2Cscope | 17442 | 18210 |
| X2Cscope module | 11625 | 11625 |
| Total | 29067 | 29835 |
| Data memory (bytes) | ||
| Excluding X2Cscope | 1672 | 1672 |
| X2Cscope module | 5186 | 5186 |
| Total | 6858 | 6858 |
| CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) | ||
| Worst-case | 2286 (45.7%) | 2247 (44.9%) |
| 99.9% percentile | 2272 (45.4%) | 2226 (44.5%) |
Algorithm options and variants — these represent additional usage costs in CPU usage, program (code) memory size, and data memory size, above the base case shown above. CPU measurements are approximate, based on capturing elapsed timer measurements from the test harness. All measurements are made from independent test cases enabling one module or option at a time, which may not take into account interaction between modules; for example, the compiler may be able to identify additional optimization opportunities if more than one of the cases below are enabled simultaneously, or the additional computations may cause additional CPU cycles for register moves that are not required when the same modules are enabled separately.
| Module | Option | CPU usage
(cycles) |
Size (bytes) | Conditions | |
|---|---|---|---|---|---|
| Code | Data | ||||
| Dead-time compensation | Per-phase | +66 | +309 | +28 | XC16 1.60 -O2, 33C
(dsPIC33CK256MP508) |
| Flux control | Equation-based, FW+MTPA disabled | +115 | +816 | +60 | XC16 1.60 -O2, 33C
(dsPIC33CK256MP508),
full-saliency forced on |
| Flux control | Equation-based, FW enabled | +407 | +1191 | +60 | XC16 1.60 -O2, 33C
(dsPIC33CK256MP508),
full-saliency forced on |
| Flux control | Equation-based, MTPA enabled | +256 | +954 | +60 | XC16 1.60 -O2, 33C
(dsPIC33CK256MP508),
full-saliency forced on |
| Flux control | Equation-based, FW+MTPA enabled | +531 | +1293 | +60 | XC16 1.60 -O2, 33C
(dsPIC33CK256MP508),
full-saliency forced on |
6.6.6. Changes between MCAF revisions¶
The apparent decrease in ISR usage between MCAF R3 and R4 should not be taken as conclusive. Microchip staff have performed similar tests where the CPU usage time has increased slightly from MCAF R3 to MCAF R4; we are aware of the issue and are investigating more reliable methods to compare CPU usage between MCAF revisions under controlled conditions.
MCAF R6 CPU usage has increased slightly compared to MCAF R5. Microchip staff is investigating causes and potential ways to reduce CPU usage in future MCAF revisions.