Frequently Asked Questions

What is the input software language to SmartHLS?

The input language to SmartHLS is C/C++. For compiling to hardware, SmartHLS supports most of C/C++, but does not support recursive functions or dynamic memory (malloc, calloc, new, etc). Also we do not support the STL C++ library (vector, map, set, etc.) and only support a subset of the C math library (see Math Library (math.h)). These unsupported software constructs can be in the software testbench portion of the code, outside of the top-level function to be compiled to hardware (see Specifying the Top-level Function).

What is the generated RTL language?

Currently, SmartHLS only supports Verilog HDL output.

Which FPGAs do you support?

How can I get technical support?

What if running my program leads to segmentation fault due to lack of available stack space?

Linux has a default stack size of 8 MBs. As a result, using more than 8 MBs of stack in your code will lead to page fault. To overcome this issue, you can do one of the following:

  1. Use the ulimit -s NEW_STACK_SIZE command in terminal to increase stack limit.
  2. Declare your large variables as static. By using the static key word, the variables are moved to heap and no longer occupy stack space.