SmartHLS 2021.1.2 Documentation

SmartHLS automatically compiles a C/C++ program into hardware described in Verilog HDL (Hardware Description Language). The generated hardware can be programmed onto an Microchip FPGA (Field-Programmable Gate Array). Hardware implemented on an FPGA can provide 2-10X performance and power benefits over the same computation running on regular processors.

The documentation is comprised of the following sections:

For example applications using SmartHLS please check out our github at:

For support, please contact smarthls@microchip.com.