Velocity Userspace
registers.h
1 /*
2  * Microsemi Switchtec(tm) PCIe Management Library
3  * Copyright (c) 2017, Microsemi Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included
13  * in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  */
24 
25 #pragma once
26 
27 #include <stdint.h>
28 
29 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
30 #define SWITCHTEC_MAX_PFF_CSR 255
31 #define SWITCHTEC_MAX_PARTITIONS 48
32 
33 #define MICROSEMI_VENDOR_ID 0x11f8
34 
35 #define BIT(x) (1 << x)
36 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
37 #define SWITCHTEC_EVENT_CLEAR BIT(0)
38 #define SWITCHTEC_EVENT_EN_LOG BIT(1)
39 #define SWITCHTEC_EVENT_EN_CLI BIT(2)
40 #define SWITCHTEC_EVENT_EN_IRQ BIT(3)
41 #define SWITCHTEC_EVENT_FATAL BIT(4)
42 
43 #ifdef MSVC
44 #pragma warning(disable: 4201)
45 #endif
46 
47 #pragma pack(push, 1)
48 
49 enum {
50  SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
51  SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
52  SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
53  SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
54  SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
55  SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
56  SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
57  SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
58 };
59 
60 struct mrpc_regs {
61  uint8_t input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
62  uint8_t output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
63  uint32_t cmd;
64  uint32_t status;
65  uint32_t ret_value;
66 };
67 
68 enum mrpc_status {
69  SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
70  SWITCHTEC_MRPC_STATUS_DONE = 2,
71  SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
72  SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
73 };
74 
75 struct top_regs {
76  uint8_t bifur_valid;
77  uint8_t stack_valid[6];
78  uint8_t partition_count;
79  uint8_t partition_id;
80  uint8_t pff_count;
81  uint8_t pff_port[255];
82 };
83 
84 struct event {
85  uint32_t hdr;
86  uint32_t data[5];
87 };
88 
89 struct sw_event_regs {
90  uint64_t event_report_ctrl;
91  uint64_t reserved1;
92  uint64_t part_event_bitmap;
93  uint64_t reserved2;
94  uint32_t global_summary;
95  uint32_t reserved3[3];
96  uint32_t stack_error_event_hdr;
97  uint32_t stack_error_event_data;
98  uint32_t reserved4[4];
99  uint32_t ppu_error_event_hdr;
100  uint32_t ppu_error_event_data;
101  uint32_t reserved5[4];
102  uint32_t isp_error_event_hdr;
103  uint32_t isp_error_event_data;
104  uint32_t reserved6[4];
105  uint32_t sys_reset_event_hdr;
106  uint32_t reserved7[5];
107  uint32_t fw_exception_hdr;
108  uint32_t reserved8[5];
109  uint32_t fw_nmi_hdr;
110  uint32_t reserved9[5];
111  uint32_t fw_non_fatal_hdr;
112  uint32_t reserved10[5];
113  uint32_t fw_fatal_hdr;
114  uint32_t reserved11[5];
115  uint32_t twi_mrpc_comp_hdr;
116  uint32_t twi_mrpc_comp_data;
117  uint32_t reserved12[4];
118  uint32_t twi_mrpc_comp_async_hdr;
119  uint32_t twi_mrpc_comp_async_data;
120  uint32_t reserved13[4];
121  uint32_t cli_mrpc_comp_hdr;
122  uint32_t cli_mrpc_comp_data;
123  uint32_t reserved14[4];
124  uint32_t cli_mrpc_comp_async_hdr;
125  uint32_t cli_mrpc_comp_async_data;
126  uint32_t reserved15[4];
127  uint32_t gpio_interrupt_hdr;
128  uint32_t gpio_interrupt_data;
129  uint32_t reserved16[4];
130  uint32_t gfms_event_hdr;
131  uint32_t gfms_event_data;
132  uint32_t reserved17[4];
133  uint32_t reserved18[60];
134  struct event customer_events[6];
135  uint32_t reserved19[320];
136 };
137 
138 enum {
139  SWITCHTEC_CFG0_RUNNING = 0x04,
140  SWITCHTEC_CFG1_RUNNING = 0x05,
141  SWITCHTEC_IMG0_RUNNING = 0x03,
142  SWITCHTEC_IMG1_RUNNING = 0x07,
143 };
144 
145 struct sys_info_regs {
146  uint32_t device_id;
147  uint32_t device_version;
148  uint32_t firmware_version;
149  uint32_t reserved1;
150  uint32_t vendor_table_revision;
151  uint32_t table_format_version;
152  uint32_t partition_id;
153  uint32_t cfg_file_fmt_version;
154  uint16_t cfg_running;
155  uint16_t img_running;
156  uint32_t reserved2[57];
157  char vendor_id[8];
158  char product_id[16];
159  char product_revision[4];
160  char component_vendor[8];
161  uint16_t component_id;
162  uint8_t component_revision;
163 };
164 
165 struct flash_info_regs {
166  uint32_t flash_part_map_upd_idx;
167 
168  struct active_partition_info {
169  uint32_t address;
170  uint32_t build_version;
171  uint32_t build_string;
172  } active_img;
173 
174  struct active_partition_info active_cfg;
175  struct active_partition_info inactive_img;
176  struct active_partition_info inactive_cfg;
177 
178  uint32_t flash_length;
179 
180  struct partition_info {
181  uint32_t address;
182  uint32_t length;
183  } cfg0;
184 
185  struct partition_info cfg1;
186  struct partition_info img0;
187  struct partition_info img1;
188  struct partition_info nvlog;
189  struct partition_info vendor[8];
190 };
191 
192 struct part_cfg_regs {
193  uint32_t status;
194  uint32_t state;
195  uint32_t port_cnt;
196  uint32_t usp_port_mode;
197  uint32_t usp_pff_inst_id;
198  uint32_t vep_pff_inst_id;
199  uint32_t dsp_pff_inst_id[47];
200  uint32_t reserved1[11];
201  uint16_t vep_vector_number;
202  uint16_t usp_vector_number;
203  uint32_t port_event_bitmap;
204  uint32_t reserved2[3];
205  uint32_t part_event_summary;
206  uint32_t reserved3[3];
207  uint32_t part_reset_hdr;
208  uint32_t part_reset_data[5];
209  uint32_t mrpc_comp_hdr;
210  uint32_t mrpc_comp_data[5];
211  uint32_t mrpc_comp_async_hdr;
212  uint32_t mrpc_comp_async_data[5];
213  uint32_t dyn_binding_hdr;
214  uint32_t dyn_binding_data[5];
215  uint32_t reserved4[120];
216  struct event customer_events[6];
217  uint32_t reserved5[3];
218 };
219 
220 enum {
221  SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
222  SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
223  SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
224 };
225 
226 struct ntb_info_regs {
227  uint8_t partition_count;
228  uint8_t partition_id;
229  uint16_t reserved1;
230  uint64_t ep_map;
231  uint16_t requester_id;
232 };
233 
234 enum {
235  NTB_CTRL_PART_OP_LOCK = 0x1,
236  NTB_CTRL_PART_OP_CFG = 0x2,
237  NTB_CTRL_PART_OP_RESET = 0x3,
238 
239  NTB_CTRL_PART_STATUS_NORMAL = 0x1,
240  NTB_CTRL_PART_STATUS_LOCKED = 0x2,
241  NTB_CTRL_PART_STATUS_LOCKING = 0x3,
242  NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
243  NTB_CTRL_PART_STATUS_RESETTING = 0x5,
244 
245  NTB_CTRL_BAR_VALID = 1 << 0,
246  NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
247  NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
248 
249  NTB_CTRL_REQ_ID_EN = 1 << 0,
250 
251  NTB_CTRL_LUT_EN = 1 << 0,
252 
253  NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
254 };
255 
256 struct ntb_ctrl_regs {
257  uint32_t partition_status;
258  uint32_t partition_op;
259  uint32_t partition_ctrl;
260  uint32_t bar_setup;
261  uint32_t bar_error;
262  uint16_t lut_table_entries;
263  uint16_t lut_table_offset;
264  uint32_t lut_error;
265  uint16_t req_id_table_size;
266  uint16_t req_id_table_offset;
267  uint32_t req_id_error;
268  uint32_t reserved1[7];
269  struct {
270  uint32_t ctl;
271  uint32_t win_size;
272  uint64_t xlate_addr;
273  } bar_entry[6];
274  uint32_t reserved2[216];
275  uint32_t req_id_table[256];
276  uint32_t reserved3[512];
277  uint64_t lut_entry[512];
278 };
279 
280 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
281 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
282 
283 struct ntb_dbmsg_regs {
284  uint32_t reserved1[1024];
285  uint64_t odb;
286  uint64_t odb_mask;
287  uint64_t idb;
288  uint64_t idb_mask;
289  uint8_t idb_vec_map[64];
290  uint32_t msg_map;
291  uint32_t reserved2;
292  struct {
293  uint32_t msg;
294  uint32_t status;
295  } omsg[4];
296 
297  struct {
298  uint32_t msg;
299  uint8_t status;
300  uint8_t mask;
301  uint8_t src;
302  uint8_t reserved;
303  } imsg[4];
304 
305  uint8_t reserved3[3928];
306  uint8_t msix_table[1024];
307  uint8_t reserved4[3072];
308  uint8_t pba[24];
309  uint8_t reserved5[4072];
310 };
311 
312 struct ntb_regs {
313  union {
314  struct ntb_info_regs info;
315  uint8_t __pad_info[SWITCHTEC_NTB_REG_CTRL_OFFSET -
316  SWITCHTEC_NTB_REG_INFO_OFFSET];
317  };
318 
319  union {
320  struct ntb_ctrl_regs ctrl[SWITCHTEC_MAX_PARTITIONS];
321  uint8_t __pad_ctrl[SWITCHTEC_NTB_REG_DBMSG_OFFSET -
322  SWITCHTEC_NTB_REG_CTRL_OFFSET];
323  };
324 
325  struct ntb_dbmsg_regs dbmsg[SWITCHTEC_MAX_PARTITIONS];
326 };
327 
328 enum {
329  SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
330  SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
331  SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
332  SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
333 };
334 
335 struct pff_csr_regs {
336  uint16_t vendor_id;
337  uint16_t device_id;
338  uint32_t pci_cfg_header[15];
339  uint32_t pci_cap_region[48];
340  uint32_t pcie_cap_region[448];
341  uint32_t indirect_gas_window[128];
342  uint32_t indirect_gas_window_off;
343  uint32_t reserved[127];
344  uint32_t pff_event_summary;
345  uint32_t reserved2[3];
346  uint32_t aer_in_p2p_hdr;
347  uint32_t aer_in_p2p_data[5];
348  uint32_t aer_in_vep_hdr;
349  uint32_t aer_in_vep_data[5];
350  uint32_t dpc_hdr;
351  uint32_t dpc_data[5];
352  uint32_t cts_hdr;
353  uint32_t cts_data[5];
354  uint32_t uec_hdr;
355  uint32_t uec_data[5];
356  uint32_t hotplug_hdr;
357  uint32_t hotplug_data[5];
358  uint32_t ier_hdr;
359  uint32_t ier_data[5];
360  uint32_t threshold_hdr;
361  uint32_t threshold_data[5];
362  uint32_t power_mgmt_hdr;
363  uint32_t power_mgmt_data[5];
364  uint32_t tlp_throttling_hdr;
365  uint32_t tlp_throttling_data[5];
366  uint32_t force_speed_hdr;
367  uint32_t force_speed_data[5];
368  uint32_t credit_timeout_hdr;
369  uint32_t credit_timeout_data[5];
370  uint32_t link_state_hdr;
371  uint32_t link_state_data[5];
372  uint32_t reserved3[66];
373  struct event customer_events[6];
374  uint32_t reserved4[72];
375 };
376 
377 struct switchtec_gas {
378  union {
379  struct mrpc_regs mrpc;
380  uint8_t __pad_mrpc[SWITCHTEC_GAS_TOP_CFG_OFFSET];
381  };
382 
383  union {
384  struct top_regs top;
385  uint8_t __pad_top_cfg[SWITCHTEC_GAS_SW_EVENT_OFFSET -
386  SWITCHTEC_GAS_TOP_CFG_OFFSET];
387  };
388 
389  union {
390  struct sw_event_regs sw_event;
391  uint8_t __pad_sw_event[SWITCHTEC_GAS_SYS_INFO_OFFSET -
392  SWITCHTEC_GAS_SW_EVENT_OFFSET];
393  };
394 
395  union {
396  struct sys_info_regs sys_info;
397  uint8_t __pad_sys_info[SWITCHTEC_GAS_FLASH_INFO_OFFSET -
398  SWITCHTEC_GAS_SYS_INFO_OFFSET];
399  };
400 
401  union {
402  struct flash_info_regs flash_info;
403  uint8_t __pad_flash_info[SWITCHTEC_GAS_PART_CFG_OFFSET -
404  SWITCHTEC_GAS_FLASH_INFO_OFFSET];
405  };
406 
407  union {
408  struct part_cfg_regs part_cfg[SWITCHTEC_MAX_PARTITIONS];
409  uint8_t __pad_part_cfg[SWITCHTEC_GAS_NTB_OFFSET -
410  SWITCHTEC_GAS_PART_CFG_OFFSET];
411  };
412 
413  union {
414  struct ntb_regs ntb;
415  uint8_t __pad_ntb[SWITCHTEC_GAS_PFF_CSR_OFFSET -
416  SWITCHTEC_GAS_NTB_OFFSET];
417  };
418 
419  struct pff_csr_regs pff_csr[SWITCHTEC_MAX_PFF_CSR];
420 };
421 
422 #pragma pack(pop)
sw_event_regs
Definition: registers.h:89
flash_info_regs::partition_info
Definition: registers.h:180
event
Definition: registers.h:84
flash_info_regs
Definition: registers.h:165
pff_csr_regs
Definition: registers.h:335
ntb_regs
Definition: registers.h:312
flash_info_regs::active_partition_info
Definition: registers.h:168
sys_info_regs
Definition: registers.h:145
part_cfg_regs
Definition: registers.h:192
sw_event_regs::gfms_event_hdr
uint32_t gfms_event_hdr
Event specific for PAX.
Definition: registers.h:130
ntb_ctrl_regs
Definition: registers.h:256
mrpc_regs
Definition: registers.h:60
switchtec_gas
Definition: registers.h:377
ntb_dbmsg_regs
Definition: registers.h:283
ntb_info_regs
Definition: registers.h:226
top_regs
Definition: registers.h:75
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