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#define | ATCA_AES_ENABLE_EN_SHIFT (0) |
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#define | ATCA_AES_ENABLE_EN_MASK (0x01u << ATCA_AES_ENABLE_EN_SHIFT) |
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#define | ATCA_I2C_ENABLE_EN_SHIFT (0) |
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#define | ATCA_I2C_ENABLE_EN_MASK (0x01u << ATCA_I2C_ENABLE_EN_SHIFT) |
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#define | ATCA_COUNTER_MATCH_EN_SHIFT (0) |
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#define | ATCA_COUNTER_MATCH_EN_MASK (0x01u << ATCA_COUNTER_MATCH_EN_SHIFT) |
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#define | ATCA_COUNTER_MATCH_KEY_SHIFT (4) |
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#define | ATCA_COUNTER_MATCH_KEY_MASK (0x0Fu << ATCA_COUNTER_MATCH_KEY_SHIFT) |
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#define | ATCA_COUNTER_MATCH_KEY(v) (ATCA_COUNTER_MATCH_KEY_MASK & (v << ATCA_COUNTER_MATCH_KEY_SHIFT)) |
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#define | ATCA_CHIP_MODE_I2C_EXTRA_SHIFT (0) |
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#define | ATCA_CHIP_MODE_I2C_EXTRA_MASK (0x01u << ATCA_CHIP_MODE_I2C_EXTRA_SHIFT) |
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#define | ATCA_CHIP_MODE_TTL_EN_SHIFT (1) |
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#define | ATCA_CHIP_MODE_TTL_EN_MASK (0x01u << ATCA_CHIP_MODE_TTL_EN_SHIFT) |
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#define | ATCA_CHIP_MODE_WDG_LONG_SHIFT (2) |
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#define | ATCA_CHIP_MODE_WDG_LONG_MASK (0x01u << ATCA_CHIP_MODE_WDG_LONG_SHIFT) |
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#define | ATCA_CHIP_MODE_CLK_DIV_SHIFT (3) |
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#define | ATCA_CHIP_MODE_CLK_DIV_MASK (0x1Fu << ATCA_CHIP_MODE_CLK_DIV_SHIFT) |
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#define | ATCA_CHIP_MODE_CLK_DIV(v) (ATCA_CHIP_MODE_CLK_DIV_MASK & (v << ATCA_CHIP_MODE_CLK_DIV_SHIFT)) |
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#define | ATCA_SLOT_CONFIG_READKEY_SHIFT (0) |
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#define | ATCA_SLOT_CONFIG_READKEY_MASK (0x0Fu << ATCA_SLOT_CONFIG_READKEY_SHIFT) |
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#define | ATCA_SLOT_CONFIG_READKEY(v) (ATCA_SLOT_CONFIG_READKEY_MASK & (v << ATCA_SLOT_CONFIG_READKEY_SHIFT)) |
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#define | ATCA_SLOT_CONFIG_NOMAC_SHIFT (4) |
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#define | ATCA_SLOT_CONFIG_NOMAC_MASK (0x01u << ATCA_SLOT_CONFIG_NOMAC_SHIFT) |
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#define | ATCA_SLOT_CONFIG_LIMITED_USE_SHIFT (5) |
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#define | ATCA_SLOT_CONFIG_LIMITED_USE_MASK (0x01u << ATCA_SLOT_CONFIG_LIMITED_USE_SHIFT) |
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#define | ATCA_SLOT_CONFIG_ENC_READ_SHIFT (6) |
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#define | ATCA_SLOT_CONFIG_ENC_READ_MASK (0x01u << ATCA_SLOT_CONFIG_ENC_READ_SHIFT) |
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#define | ATCA_SLOT_CONFIG_IS_SECRET_SHIFT (7) |
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#define | ATCA_SLOT_CONFIG_IS_SECRET_MASK (0x01u << ATCA_SLOT_CONFIG_IS_SECRET_SHIFT) |
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#define | ATCA_SLOT_CONFIG_WRITE_KEY_SHIFT (8) |
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#define | ATCA_SLOT_CONFIG_WRITE_KEY_MASK ((uint32_t)0x0Fu << ATCA_SLOT_CONFIG_WRITE_KEY_SHIFT) |
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#define | ATCA_SLOT_CONFIG_WRITE_KEY(v) (ATCA_SLOT_CONFIG_WRITE_KEY_MASK & (v << ATCA_SLOT_CONFIG_WRITE_KEY_SHIFT)) |
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#define | ATCA_SLOT_CONFIG_WRITE_CONFIG_SHIFT (12) |
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#define | ATCA_SLOT_CONFIG_WRITE_CONFIG_MASK (((uint32_t)0x0Fu << ATCA_SLOT_CONFIG_WRITE_CONFIG_SHIFT)) |
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#define | ATCA_SLOT_CONFIG_WRITE_CONFIG(v) ((ATCA_SLOT_CONFIG_WRITE_CONFIG_MASK & ((uint32_t)(v) << ATCA_SLOT_CONFIG_WRITE_CONFIG_SHIFT))) |
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#define | ATCA_SLOT_CONFIG_EXT_SIG_SHIFT (0) |
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#define | ATCA_SLOT_CONFIG_EXT_SIG_MASK (0x01u << ATCA_SLOT_CONFIG_EXT_SIG_SHIFT) |
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#define | ATCA_SLOT_CONFIG_INT_SIG_SHIFT (1) |
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#define | ATCA_SLOT_CONFIG_INT_SIG_MASK (0x01u << ATCA_SLOT_CONFIG_INT_SIG_SHIFT) |
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#define | ATCA_SLOT_CONFIG_ECDH_SHIFT (2) |
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#define | ATCA_SLOT_CONFIG_ECDH_MASK (0x01u << ATCA_SLOT_CONFIG_ECDH_SHIFT) |
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#define | ATCA_SLOT_CONFIG_WRITE_ECDH_SHIFT (3) |
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#define | ATCA_SLOT_CONFIG_WRITE_ECDH_MASK (0x01u << ATCA_SLOT_CONFIG_WRITE_ECDH_SHIFT) |
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#define | ATCA_SLOT_CONFIG_GEN_KEY_SHIFT (8) |
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#define | ATCA_SLOT_CONFIG_GEN_KEY_MASK (0x01u << ATCA_SLOT_CONFIG_GEN_KEY_SHIFT) |
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#define | ATCA_SLOT_CONFIG_PRIV_WRITE_SHIFT (9) |
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#define | ATCA_SLOT_CONFIG_PRIV_WRITE_MASK (0x01u << ATCA_SLOT_CONFIG_PRIV_WRITE_SHIFT) |
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#define | ATCA_USE_LOCK_ENABLE_SHIFT (0) |
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#define | ATCA_USE_LOCK_ENABLE_MASK (0x0Fu << ATCA_USE_LOCK_ENABLE_SHIFT) |
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#define | ATCA_USE_LOCK_KEY_SHIFT (4) |
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#define | ATCA_USE_LOCK_KEY_MASK (0x0Fu << ATCA_USE_LOCK_KEY_SHIFT) |
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#define | ATCA_VOL_KEY_PERM_SLOT_SHIFT (0) |
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#define | ATCA_VOL_KEY_PERM_SLOT_MASK (0x0Fu << ATCA_VOL_KEY_PERM_SLOT_SHIFT) |
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#define | ATCA_VOL_KEY_PERM_SLOT(v) (ATCA_VOL_KEY_PERM_SLOT_MASK & (v << ATCA_VOL_KEY_PERM_SLOT_SHIFT)) |
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#define | ATCA_VOL_KEY_PERM_EN_SHIFT (7) |
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#define | ATCA_VOL_KEY_PERM_EN_MASK (0x01u << ATCA_VOL_KEY_PERM_EN_SHIFT) |
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#define | ATCA_SECURE_BOOT_MODE_SHIFT (0) |
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#define | ATCA_SECURE_BOOT_MODE_MASK (0x03u << ATCA_SECURE_BOOT_MODE_SHIFT) |
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#define | ATCA_SECURE_BOOT_MODE(v) (ATCA_SECURE_BOOT_MODE_MASK & (v << ATCA_SECURE_BOOT_MODE_SHIFT)) |
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#define | ATCA_SECURE_BOOT_PERSIST_EN_SHIFT (3) |
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#define | ATCA_SECURE_BOOT_PERSIST_EN_MASK (0x01u << ATCA_SECURE_BOOT_PERSIST_EN_SHIFT) |
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#define | ATCA_SECURE_BOOT_RAND_NONCE_SHIFT (4) |
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#define | ATCA_SECURE_BOOT_RAND_NONCE_MASK (0x01u << ATCA_SECURE_BOOT_RAND_NONCE_SHIFT) |
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#define | ATCA_SECURE_BOOT_DIGEST_SHIFT (8) |
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#define | ATCA_SECURE_BOOT_DIGEST_MASK (0x0Fu << ATCA_SECURE_BOOT_DIGEST_SHIFT) |
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#define | ATCA_SECURE_BOOT_DIGEST(v) (ATCA_SECURE_BOOT_DIGEST_MASK & (v << ATCA_SECURE_BOOT_DIGEST_SHIFT)) |
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#define | ATCA_SECURE_BOOT_PUB_KEY_SHIFT (12) |
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#define | ATCA_SECURE_BOOT_PUB_KEY_MASK (0x0Fu << ATCA_SECURE_BOOT_PUB_KEY_SHIFT) |
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#define | ATCA_SECURE_BOOT_PUB_KEY(v) (ATCA_SECURE_BOOT_PUB_KEY_MASK & (v << ATCA_SECURE_BOOT_PUB_KEY_SHIFT)) |
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#define | ATCA_SLOT_LOCKED(v) ((0x01 << v) & 0xFFFFu) |
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#define | ATCA_CHIP_OPT_POST_EN_SHIFT (0) |
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#define | ATCA_CHIP_OPT_POST_EN_MASK (0x01u << ATCA_CHIP_OPT_POST_EN_SHIFT) |
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#define | ATCA_CHIP_OPT_IO_PROT_EN_SHIFT (1) |
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#define | ATCA_CHIP_OPT_IO_PROT_EN_MASK (0x01u << ATCA_CHIP_OPT_IO_PROT_EN_SHIFT) |
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#define | ATCA_CHIP_OPT_KDF_AES_EN_SHIFT (2) |
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#define | ATCA_CHIP_OPT_KDF_AES_EN_MASK (0x01u << ATCA_CHIP_OPT_KDF_AES_EN_SHIFT) |
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#define | ATCA_CHIP_OPT_ECDH_PROT_SHIFT (8) |
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#define | ATCA_CHIP_OPT_ECDH_PROT_MASK (0x03u << ATCA_CHIP_OPT_ECDH_PROT_SHIFT) |
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#define | ATCA_CHIP_OPT_ECDH_PROT(v) (ATCA_CHIP_OPT_ECDH_PROT_MASK & (v << ATCA_CHIP_OPT_ECDH_PROT_SHIFT)) |
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#define | ATCA_CHIP_OPT_KDF_PROT_SHIFT (10) |
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#define | ATCA_CHIP_OPT_KDF_PROT_MASK (0x03u << ATCA_CHIP_OPT_KDF_PROT_SHIFT) |
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#define | ATCA_CHIP_OPT_KDF_PROT(v) (ATCA_CHIP_OPT_KDF_PROT_MASK & (v << ATCA_CHIP_OPT_KDF_PROT_SHIFT)) |
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#define | ATCA_CHIP_OPT_IO_PROT_KEY_SHIFT (12) |
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#define | ATCA_CHIP_OPT_IO_PROT_KEY_MASK ((uint16_t)0x0Fu << ATCA_CHIP_OPT_IO_PROT_KEY_SHIFT) |
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#define | ATCA_CHIP_OPT_IO_PROT_KEY(v) (ATCA_CHIP_OPT_IO_PROT_KEY_MASK & (v << ATCA_CHIP_OPT_IO_PROT_KEY_SHIFT)) |
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#define | ATCA_KEY_CONFIG_OFFSET(x) (96UL + (x) * 2u) |
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#define | ATCA_KEY_CONFIG_PRIVATE_SHIFT (0) |
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#define | ATCA_KEY_CONFIG_PRIVATE_MASK (0x01u << ATCA_KEY_CONFIG_PRIVATE_SHIFT) |
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#define | ATCA_KEY_CONFIG_PUB_INFO_SHIFT (1) |
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#define | ATCA_KEY_CONFIG_PUB_INFO_MASK (0x01u << ATCA_KEY_CONFIG_PUB_INFO_SHIFT) |
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#define | ATCA_KEY_CONFIG_KEY_TYPE_SHIFT (2) |
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#define | ATCA_KEY_CONFIG_KEY_TYPE_MASK ((0x07u << ATCA_KEY_CONFIG_KEY_TYPE_SHIFT)) |
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#define | ATCA_KEY_CONFIG_KEY_TYPE(v) ((ATCA_KEY_CONFIG_KEY_TYPE_MASK & ((v) << ATCA_KEY_CONFIG_KEY_TYPE_SHIFT))) |
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#define | ATCA_KEY_CONFIG_LOCKABLE_SHIFT (5) |
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#define | ATCA_KEY_CONFIG_LOCKABLE_MASK (0x01u << ATCA_KEY_CONFIG_LOCKABLE_SHIFT) |
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#define | ATCA_KEY_CONFIG_REQ_RANDOM_SHIFT (6) |
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#define | ATCA_KEY_CONFIG_REQ_RANDOM_MASK (0x01u << ATCA_KEY_CONFIG_REQ_RANDOM_SHIFT) |
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#define | ATCA_KEY_CONFIG_REQ_AUTH_SHIFT (7) |
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#define | ATCA_KEY_CONFIG_REQ_AUTH_MASK (0x01u << ATCA_KEY_CONFIG_REQ_AUTH_SHIFT) |
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#define | ATCA_KEY_CONFIG_AUTH_KEY_SHIFT (8) |
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#define | ATCA_KEY_CONFIG_AUTH_KEY_MASK (0x0Fu << ATCA_KEY_CONFIG_AUTH_KEY_SHIFT) |
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#define | ATCA_KEY_CONFIG_AUTH_KEY(v) (ATCA_KEY_CONFIG_AUTH_KEY_MASK & (v << ATCA_KEY_CONFIG_AUTH_KEY_SHIFT)) |
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#define | ATCA_KEY_CONFIG_PERSIST_DIS_SHIFT (12) |
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#define | ATCA_KEY_CONFIG_PERSIST_DIS_MASK (0x01u << ATCA_KEY_CONFIG_PERSIST_DIS_SHIFT) |
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#define | ATCA_KEY_CONFIG_RFU_SHIFT (13) |
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#define | ATCA_KEY_CONFIG_RFU_MASK (0x01u << ATCA_KEY_CONFIG_RFU_SHIFT) |
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#define | ATCA_KEY_CONFIG_X509_ID_SHIFT (14) |
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#define | ATCA_KEY_CONFIG_X509_ID_MASK (0x03u << ATCA_KEY_CONFIG_X509_ID_SHIFT) |
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#define | ATCA_KEY_CONFIG_X509_ID(v) (ATCA_KEY_CONFIG_X509_ID_MASK & (v << ATCA_KEY_CONFIG_X509_ID_SHIFT)) |
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- (c) 2015-2020 Microchip Technology Inc. and its subsidiaries.