6.7. Resource Usage¶
This section provides reference data for resource usage, covering program and data memory and CPU usage.
Please note: Resource usage is dependent on a number of factors, and may be different than the data shown below. These factors include:
Compiler version
Compiler optimization levels
Compiler flags
Settings in motorBench® Development Suite
Settings in MCC
MCAF parameter values
6.7.1. Test case¶
In each case described below, MCAF firmware packages were used with default settings and the AN1292
PLL estimator selected, using the Nidec Hurst DMA0204024B101 motor and the dsPICDEM® MCLV‑2 Development Board. The source code was built using
both XC16 and XC-DSC with -O1 and -O2 compilation levels for the devices dsPIC33EP256MC506,
dsPIC33CK256MP508, and dsPIC33CK64MC105. The macros MCAF_TEST_PROFILING and MCAF_TEST_HARNESS
were enabled in options.h (see Profiling timestamps).
6.7.1.1. Program and data memory¶
Resource usage statistics for program and data memory were derived from the map file.
6.7.1.2. CPU usage¶
CPU usage was determined with variants of MCAF modified to transmit CPU cycle count data via the UART, at various points in the motor control ISR, for a 20 kHz PWM ISR, using dsPIC33CK256MP508 and dsPIC33CK64MC105 running at 100 MIPS, and dsPIC33EP256MC506 running at 70 MIPS.
CPU cycle count was measured over approximately 4 seconds, with the motor starting up, running, and slowing to a stop. The resulting time inside the motor control ISR was sorted from low to high, with the worst-case and 99.9% percentile computed. For example, 4 seconds of data at 20 kHz represents 80,000 data points, so the 99.9% percentile represents the 80th-highest sample of CPU usage. This represents conservative estimates of CPU usage for estimating remaining CPU capacity in aggregate over time, and exclude timing spikes which may occur when long execution paths coincide in the same ISR cycle. The worst-case CPU usage should be used to determine that the ISR does not exceed available CPU time. Variation in CPU time is due to a number of factors, including:
Branches (
ifstatements) may take alternate and unequal execution pathsSome algorithms run at submultiples of the ISR, so for example the PLL position estimator has a portion of code that runs once every 8 ISR cycles
During different states of the state machine, different parts of the code are enabled or disabled
Main loop CPU usage was not profiled but is minimal (estimated at < 0.1 MIPS); not much code runs in the main loop.
6.7.2. Usage statistics for MCAF R3¶
Statistic |
MCAF R3, XC16 1.35 |
MCAF R3, XC16 1.35 |
|---|---|---|
Program memory (bytes) |
||
Excluding X2Cscope |
20367 |
21744 |
X2Cscope module |
12831 |
12831 |
Total |
33198 |
34575 |
Data memory (bytes) |
||
Excluding X2Cscope |
1342 |
1340 |
X2Cscope module |
5466 |
5466 |
Total |
6808 |
6806 |
CPU ISR usage (% at 70 MIPS, 20 kHz ISR) |
||
Worst-case |
64.1% |
62.9% |
99.9% percentile |
63.8% |
62.6% |
6.7.3. Usage statistics for MCAF R4¶
Statistic |
MCAF R4, XC16 1.36b |
MCAF R4, XC16 1.36b |
|---|---|---|
Program memory (bytes) |
||
Excluding X2Cscope |
17556 |
18150 |
X2Cscope module |
12831 |
12753 |
Total |
30309 |
30903 |
Data memory (bytes) |
||
Excluding X2Cscope |
1402 |
1402 |
X2Cscope module |
5448 |
5448 |
Total |
6850 |
6850 |
CPU ISR usage (% at 70 MIPS, 20 kHz ISR) |
||
Worst-case |
58.9% |
58.1% |
99.9% percentile |
58.9% |
58.1% |
6.7.4. Usage statistics for MCAF R5¶
Statistic |
MCAF R5, XC16 1.41 |
MCAF R5, XC16 1.41 |
|---|---|---|
Program memory (bytes) |
||
Excluding X2Cscope |
17334 |
18783 |
X2Cscope module |
11709 |
11709 |
Total |
29043 |
30492 |
Data memory (bytes) |
||
Excluding X2Cscope |
1528 |
1580 |
X2Cscope module |
5186 |
5186 |
Total |
6714 |
6766 |
CPU ISR usage (% at 70 MIPS, 20 kHz ISR) |
||
Worst-case |
58.3% |
57.6% |
99.9% percentile |
57.8% |
57.0% |
6.7.5. Usage statistics for MCAF R6¶
dsPIC33EP256MC506
Statistic |
MCAF R6, XC16 1.60 |
MCAF R6, XC16 1.60 |
|---|---|---|
Program memory (bytes) |
||
Excluding X2Cscope |
17376 |
18219 |
X2Cscope module |
11709 |
11709 |
Total |
29916 |
30885 |
Data memory (bytes) |
||
Excluding X2Cscope |
1672 |
1672 |
X2Cscope module |
5186 |
5186 |
Total |
6858 |
6858 |
CPU ISR usage (approximate number of cycles, and percentage at 70 MIPS, 20 kHz ISR) |
||
Worst-case |
2330 (66.5%) |
2280 (65.2%) |
99.9% percentile |
2300 (65.8%) |
2260 (64.6%) |
dsPIC33CK256MP508
Statistic |
MCAF R6, XC16 1.60 |
MCAF R6, XC16 1.60 |
|---|---|---|
Program memory (bytes) |
||
Excluding X2Cscope |
17442 |
18210 |
X2Cscope module |
11625 |
11625 |
Total |
29067 |
29835 |
Data memory (bytes) |
||
Excluding X2Cscope |
1672 |
1672 |
X2Cscope module |
5186 |
5186 |
Total |
6858 |
6858 |
CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) |
||
Worst-case |
2286 (45.7%) |
2247 (44.9%) |
99.9% percentile |
2272 (45.4%) |
2226 (44.5%) |
Algorithm options and variants — these represent additional usage costs in CPU usage, program (code) memory size, and data memory size, above the base case shown above. CPU measurements are approximate, based on capturing elapsed timer measurements from the test harness. All measurements are made from independent test cases enabling one module or option at a time, which may not take into account interaction between modules; for example, the compiler may be able to identify additional optimization opportunities if more than one of the cases below are enabled simultaneously, or the additional computations may cause additional CPU cycles for register moves that are not required when the same modules are enabled separately.
Module |
Option |
CPU usage
|
Size (bytes) |
Conditions |
|
|---|---|---|---|---|---|
Code |
Data |
||||
Per-phase |
+66 |
+309 |
+28 |
XC16 1.60 |
|
Equation-based, FW+MTPA disabled |
+115 |
+816 |
+60 |
XC16 1.60 |
|
Equation-based, FW enabled |
+407 |
+1191 |
+60 |
XC16 1.60 |
|
Equation-based, MTPA enabled |
+256 |
+954 |
+60 |
XC16 1.60 |
|
Equation-based, FW+MTPA enabled |
+531 |
+1293 |
+60 |
XC16 1.60 |
|
6.7.6. Usage statistics for MCAF R7¶
dsPIC33EP256MC506
Statistic |
MCAF R7, XC16 2.10 |
|
|---|---|---|
|
|
|
Program memory (bytes) |
||
Excluding X2Cscope |
18753 |
19437 |
X2Cscope module |
11787 |
11787 |
Total |
30540 |
31260 |
Data memory (bytes) |
||
Excluding X2Cscope |
1532 |
1532 |
X2Cscope module |
5378 |
5378 |
Total |
6910 |
6910 |
CPU ISR usage (approximate number of cycles, and percentage at 70 MIPS, 20 kHz ISR) |
||
Worst-case |
2379 (68.0%) |
2341 (66.9%) |
99.9% percentile |
2295 (65.6%) |
2230 (63.7%) |
dsPIC33CK256MP508
Statistic |
MCAF R7, XC16 2.10 |
MCAF R7, XC16 1.60 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
17802 |
18471 |
18621 |
19353 |
X2Cscope module |
11703 |
11703 |
11703 |
11703 |
Total |
29505 |
30174 |
30324 |
31056 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1534 |
1534 |
1588 |
1588 |
X2Cscope module |
5378 |
5378 |
5378 |
5378 |
Total |
6912 |
6912 |
6966 |
6966 |
CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) |
||||
Worst-case |
2335 (46.7%) |
2273 (45.5%) |
2322 (46.4%) |
2276 (45.5%) |
99.9% percentile |
2263 (45.3%) |
2201 (44.0%) |
2307 (46.1%) |
2255 (45.1%) |
dsPIC33CK64MC105
Statistic |
MCAF R7, XC16 2.10 |
|
|---|---|---|
|
|
|
Program memory (bytes) |
||
Excluding X2Cscope |
17430 |
18108 |
X2Cscope module |
11703 |
11703 |
Total |
29133 |
29811 |
Data memory (bytes) |
||
Excluding X2Cscope |
1534 |
1534 |
X2Cscope module |
5378 |
5378 |
Total |
6912 |
6912 |
CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) |
||
Worst-case |
2333 (46.7%) |
2274 (45.5%) |
99.9% percentile |
2263 (45.3%) |
2201 (44.0%) |
Algorithm options and variants — these represent additional usage costs in CPU usage, program (code) memory size, and data memory size, above the base case shown above. CPU measurements are approximate, based on capturing elapsed timer measurements from the test harness. All measurements are made from independent test cases enabling one module or option at a time, which may not take into account interaction between modules; for example, the compiler may be able to identify additional optimization opportunities if more than one of the cases below are enabled simultaneously, or the additional computations may cause additional CPU cycles for register moves that are not required when the same modules are enabled separately.
Module |
Option |
CPU usage
|
Size (bytes) |
Conditions |
|
|---|---|---|---|---|---|
Code |
Data |
||||
Single-channel |
+222 |
+2028 |
+52 |
XC16 2.10 |
|
Triple-channel |
+100 |
+294 |
+6 |
XC16 2.10 |
|
Simple |
+113 |
+561 |
+26 |
XC16 2.10 |
|
ZS/MT standalone estimator |
-264 |
-696 |
+6 |
XC16 2.10 |
|
Binary hard-switch hybrid estimator |
+386 |
+2763 |
+130 |
XC16 2.10 |
|
6.7.7. Usage Statistics for MCAF R8¶
dsPIC33EP256MC506
Statistic |
MCAF R8, XC16 2.10 |
MCAF R8, XC-DSC 3.21 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
19092 |
19929 |
19394 |
19869 |
X2Cscope module |
11553 |
11532 |
11559 |
11538 |
Total |
30645 |
31461 |
30954 |
31407 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1536 |
1536 |
1536 |
1536 |
X2Cscope module |
5380 |
5380 |
5380 |
5380 |
Total |
6916 |
6916 |
6916 |
6916 |
CPU ISR usage (approximate number of cycles, and percentage at 70 MIPS, 20 kHz ISR) |
||||
Worst-case |
2851 (81.5%) |
2701 (77.2%) |
2841 (81.2%) |
2773 (79.2%) |
99.9% percentile |
2674 (76.4%) |
2615 (74.7%) |
2750 (78.6%) |
2686 (76.7%) |
dsPIC33CK256MP508
Statistic |
MCAF R8, XC16 2.10 |
MCAF R8, XC-DSC 3.21 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
25248 |
26163 |
26034 |
26400 |
X2Cscope module |
11514 |
11493 |
11517 |
11496 |
Total |
36762 |
37656 |
37551 |
37896 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1540 |
1540 |
1538 |
1538 |
X2Cscope module |
5380 |
5380 |
5380 |
5380 |
Total |
6920 |
6920 |
6918 |
6918 |
CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) |
||||
Worst-case |
2760 (55.2%) |
2694 (53.9%) |
2802 (56.0%) |
2761 (55.2%) |
99.9% percentile |
2570 (51.4%) |
2509 (50.2%) |
2715 (54.3%) |
2653 (53.1%) |
dsPIC33CK64MC105
Statistic |
MCAF R8, XC16 2.10 |
MCAF R8, XC-DSC 3.21 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
23925 |
24840 |
24684 |
25035 |
X2Cscope module |
11514 |
11493 |
11517 |
11496 |
Total |
35439 |
36333 |
36201 |
36531 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1540 |
1540 |
1538 |
1538 |
X2Cscope module |
5380 |
5380 |
5380 |
5380 |
Total |
6920 |
6920 |
6918 |
6918 |
CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) |
||||
Worst-case |
2661 (53.2%) |
2628 (52.6%) |
2901 (58.0%) |
2897 (57.9%) |
99.9% percentile |
2574 (51.5%) |
2512 (50.2%) |
2715 (54.3%) |
2711 (54.2%) |
6.7.8. Usage Statistics for MCAF R9¶
Note
In execution-time testing for MCAF R9, dsPIC33A and dsPIC33C devices use MCC Melody, while dsPIC33E devices use MCC Classic.
dsPIC33EP256MC506
Statistic |
MCAF R9, XC-DSC 3.21 |
MCAF R9, XC-DSC 3.31 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
19356 |
19599 |
19698 |
19977 |
X2Cscope module |
11559 |
11538 |
11556 |
11535 |
Total |
30915 |
31137 |
31254 |
31512 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1536 |
1536 |
1536 |
1536 |
X2Cscope module |
5380 |
5380 |
5380 |
5380 |
Total |
6916 |
6916 |
6916 |
6916 |
CPU ISR usage (approximate number of cycles, and percentage at 70 MIPS, 20 kHz ISR) |
||||
Worst-case |
2881 (82.3%) |
2726 (77.9%) |
2890 (82.6%) |
2744 (78.4%) |
99.9% percentile |
2718 (77.7%) |
2649 (75.7%) |
2734 (78.1%) |
2642 (75.5%) |
dsPIC33CK256MP508
Statistic |
MCAF R9, XC-DSC 3.21 |
MCAF R9, XC-DSC 3.31 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
26334 |
26526 |
26652 |
26781 |
X2Cscope module |
11517 |
11496 |
11517 |
11496 |
Total |
37851 |
38022 |
38169 |
38227 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1538 |
1538 |
1538 |
1538 |
X2Cscope module |
5380 |
5380 |
5380 |
5380 |
Total |
6918 |
6918 |
6918 |
6918 |
CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) |
||||
Worst-case |
2704 (54.1%) |
2619 (52.4%) |
2714 (54.3%) |
2642 (52.8%) |
99.9% percentile |
2609 (52.2%) |
2531 (50.6%) |
2631 (52.6%) |
2546 (50.9%) |
dsPIC33CK64MC105
Statistic |
MCAF R9, XC-DSC 3.21 |
MCAF R9, XC-DSC 3.31 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
24987 |
25164 |
25305 |
25425 |
X2Cscope module |
11517 |
11496 |
11517 |
11496 |
Total |
36504 |
36660 |
36822 |
36921 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1538 |
1538 |
1538 |
1538 |
X2Cscope module |
5380 |
5380 |
5380 |
5380 |
Total |
6918 |
6918 |
6918 |
6918 |
CPU ISR usage (approximate number of cycles, and percentage at 100 MIPS, 20 kHz ISR) |
||||
Worst-case |
2780 (55.6%) |
2629 (52.6%) |
– |
– |
99.9% percentile |
2606 (52.1%) |
2528 (50.6%) |
– |
– |
Note
CPU ISR usage results for dsPIC33CK64MC105 with the XC-DSC 3.31 compiler are not available due to technical issues in profiling this configuration; MCAF team will update these results when the profiling issues are addressed
dsPIC33AK128MC106
Statistic |
MCAF R9, XC-DSC 3.21 |
MCAF R9, XC-DSC 3.31 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
39882 |
40566 |
39480 |
40608 |
X2Cscope module |
17940 |
17892 |
17970 |
17922 |
Total |
57822 |
58458 |
57450 |
58530 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1704 |
1704 |
1704 |
1704 |
X2Cscope module |
5540 |
5540 |
5540 |
5540 |
Total |
7244 |
7244 |
7244 |
7244 |
CPU ISR usage (approximate number of cycles, and percentage at 200 MIPS, 20 kHz ISR) |
||||
Worst-case |
3358 (33.6%) |
3254 (32.5%) |
3282 (32.8%) |
3242 (32.4%) |
99.9% percentile |
3204 (32.0%) |
3136 (31.4%) |
3178 (31.8%) |
3070 (30.7%) |
dsPIC33AK512MC510
Statistic |
MCAF R9, XC-DSC 3.21 |
MCAF R9, XC-DSC 3.31 |
||
|---|---|---|---|---|
|
|
|
|
|
Program memory (bytes) |
||||
Excluding X2Cscope |
42354 |
42966 |
41946 |
43014 |
X2Cscope module |
17940 |
17892 |
17970 |
17922 |
Total |
60294 |
60858 |
59916 |
60936 |
Data memory (bytes) |
||||
Excluding X2Cscope |
1720 |
1720 |
1720 |
1720 |
X2Cscope module |
5540 |
5540 |
5540 |
5540 |
Total |
7260 |
7260 |
7260 |
7260 |
CPU ISR usage (approximate number of cycles, and percentage at 200 MIPS, 20 kHz ISR) |
||||
Worst-case |
3316 (33.2%) |
3180 (31.8%) |
3284 (32.8%) |
3186 (31.9%) |
99.9% percentile |
3182 (31.8%) |
3070 (30.7%) |
3184 (31.8%) |
3094 (30.9%) |
6.7.9. Changes between MCAF revisions¶
The apparent decrease in ISR usage between MCAF R3 and R4 should not be taken as conclusive. Microchip staff have performed similar tests where the CPU usage time has increased slightly from MCAF R3 to MCAF R4; we are aware of the issue and are investigating more reliable methods to compare CPU usage between MCAF revisions under controlled conditions.
MCAF R6 and R7 have each increased CPU usage slightly, compared to MCAF R5.
CPU usage has increased slightly in MCAF R8 compared to MCAF R7.
Microchip staff is investigating potential ways to reduce these increases in CPU usage in future MCAF revisions.