Overview

Smart high-level synthesis (SmartHLS) Compiler is an Eclipse-based integrated development environment that takes C++ software code as input and generates a SmartDesign IP component (Verilog HDL) as output. Hardware engineers can instantiate the generated SmartDesign IP component in the SmartDesign canvas available in Libero SoC design suite to build an FPGA system.

SmartHLS automatically compiles a C/C++ program into hardware described in Verilog HDL (Hardware Description Language). The generated hardware can be programmed onto an Microchip FPGA (Field-Programmable Gate Array). Hardware implemented on an FPGA can provide 2-10X performance and power benefits over the same computation running on regular processors.

SmartHLS includes C/C++ to Verilog high-level synthesis tool and is tested on Windows and Linux 64-bit Operating systems.

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The following table describes each document shipped with SmartHLS.

Document Title	Description
Getting Started	Installation and a quick start guide
User Guide	How to use SmartHLS to generate hardware
Optimization Guide	How to optimize the generated hardware
Hardware Architecture	Synthesized hardware architecture
SmartHLS Pragmas Manual	Pragmas manual
Constraints Manual	Constraints manual
SmartHLS License	How to obtain a free license for SmartHLS
Supported FPGA Devices	Supported FPGA devices
Frequently Asked Questions	SmartHLS Migration Guide
SmartHLS Migration Guide	Frequently asked questions
Release Notes	New features and known problems with each release
Technical Support	How to create tech support cases and post to our forum

For detailed trainings on using SmartHLS and example applications, see our GitHub Examples repository.