Frequently Asked Questions

What is the input software language to SmartHLS?

The input language to SmartHLS is C/C++. For compiling to hardware, SmartHLS supports most of C/C++, but does not support recursive functions or dynamic memory (malloc, calloc, new, etc). Also we do not support the STL C++ library (vector, map, set, etc.) and only support a subset of the C math library (see c_numerics_library). These unsupported software constructs can be in the software testbench portion of the code, outside of the top-level function to be compiled to hardware (see Specifying the Top-level Function).

What is the generated RTL language?

Currently, SmartHLS only supports Verilog HDL output.

Which FPGAs do you support?

SmartHLS supports Microchip PolarFire FPGAs.

How can I get support?

Please create a tech support case at microchipsupport.force.com/s/ or post a question on the Microchip forum at www.microchip.com/forums/f559.aspx.