SmartHLS 2021.1.2 Documentation

SmartHLS automatically compiles a C/C++ program into hardware described in Verilog HDL (Hardware Description Language). The generated hardware can be programmed onto an Microchip FPGA (Field-Programmable Gate Array). Hardware implemented on an FPGA can provide 2-10X performance and power benefits over the same computation running on regular processors.

The documentation is comprised of the following sections:

• Getting Started: Installation and a quick start guide

• User Guide: How to use SmartHLS to generate hardware

• Optimization Guide: How to optimize the generated hardware

• Hardware Architecture: Synthesized hardware architecture

• SmartHLS Pragmas Manual: Pragmas manual

• Constraints Manual: Constraints manual

• Frequently Asked Questions: Frequently asked questions

• Release Notes: New features and known problems with each release

For example applications using SmartHLS please check out our github at:

• https://github.com/MicrochipTech/fpga-hls-examples

For support, please contact smarthls@microchip.com.